Semiconductor device with flexible redundancy system

ABSTRACT

A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches-an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a semiconductor device with a flexibleredundancy system for saving a defective memory cell.

[0002] Semiconductor devices have a redundancy system. To enhance theyield of products, the redundancy system saves a defective memory cell,if any, by replacing it with a redundancy cell. The redundancy systemthat is most generally used at the present stage performs suchreplacement in units of a cell array, more specifically in units of aplurality of rows or columns (there is a case where it is done in unitsof one row or column). If in this system, a defective memory cell isfound after a test, a cell array including the defective cell isreplaced with a redundancy cell array (spare element) of the same size.

[0003] Address information on a cell array including the defective cellis stored in a non-volatile storage element. A fuse is generally used asthe storage element at the present stage. Since the address informationis usually formed of several bits, a fuse set which includes a pluralityof fuses corresponding to the address information is a unit ofredundancy. Further, usually, one spare element corresponds to one fuseset, and the same number of fuse sets as:the spare elements are employedin a chip. When using a spare element, a fuse included in a fuse setcorresponding thereto is cut. Since this system is of a simplestructure, it is widely used now.

[0004] On the other hand, the redundancy system requires a spare elementand a fuse set in addition to a usual circuit, and hence requires alarge chip area. In light of the fact that the area of a redundancycircuit and the number of defective cells which the redundancy circuitcan save have a trade-off relationship, various types of redundancysystems are now proposed for enhancing the area efficiency. For example,Kirihata et al. propose a flexible redundancy system (see“Fault-Tolerant Designs for 256 Mb DRAM” (IEEE JOURNAL of SOLID-STATECIRCUITS, VOL. 31, NO. 4, Apr. 1996)). Since in this system, a singlespare element covers a wide cell array area, even when defective cellsexist in only a part of a chip, they can be saved in a similar manner toa case where defective cells are uniformly dispersed within a cellarray. Accordingly, the number of spare elements can be reduced, therebyincreasing the area efficiency of the redundancy circuit.

[0005] As described above, where the number of defective cells per onechip is detected or can be estimated, to save them using a small numberof spare elements can increase the area efficiency and hence be moreeffective. In particular, where a single spare element can cover a widecell array area, the above system is effective.

[0006] However, memory chips in which a memory cell array is dividedinto portions have been developed. For example, there is a memory chipprovided with a plurality of banks which are simultaneously activated.This type of memory chip cannot have a spare element for saving adefective cell which is included in any other bank. The larger thenumber of banks, the larger the number of divisions of a memory cellarray, and the narrower the cell array area that each spare element cancover. Although this is mainly a problem of a row spare element, asimilar problem will occur at a column spare element. Moreover, if inmemory devices operable at high speed, the distance between a memorycell and another replaced by a spare element becomes longer than beforethe replacement, transmission delay of a signal or data becomes greater,thereby degrading the high speed operability. On the other hand, tomaintain the high speed operability, replacement must be performedbetween memory cells located close to each other. This means that thecolumn spare element cannot cover a wide cell array area.

[0007] When the spare element can cover only a narrow range from thelimitations such as the number of banks, the high speed operability,etc., a spare element must be provided in units of one narrow cell arrayarea to save even defective cells located at only a part of a memorycell. This means that a great number of spare elements, whichsignificantly exceeds the average number of defective cells, must beincorporated in one chip, thereby degrading the area efficiency.Moreover, in the conventional system in which one spare elementcorresponds to one fuse set, the number of fuse sets inevitablyincreases with an increase in the number of spare elements. Since, ingeneral, fuses require a larger area than spare elements, the system inwhich one spare element corresponds to one fuse set results in a largedecrease in the area efficiency of the redundancy circuit.

BRIEF SUMMARY OF THE INVENTION

[0008] This invention has been developed to solve the above-describedproblems, and has its object to provide a semiconductor device thatemploys a redundancy circuit of a high saving efficiency and a high areaefficiency on a chip, in which the redundancy circuit requires only asmall number of non-volatile storage elements to save a defective memorycell.

[0009] The object is realized by a device as below.

[0010] A semiconductor storage device comprising:

[0011] a memory cell array having memory cells arranged in columns androws, the memory cell array being divided into a plurality of sub cellarrays; redundancy cell arrays each located adjacent to a correspondingone of the sub cell arrays; row decoders for each selecting acorresponding one of the rows of the memory cell array in accordancewith an input address; column decoders for each selecting acorresponding one of the columns of the memory cell array in accordancewith an input address; a plurality of storage circuits for storingaddresses assigned to defective memory cells included in the memory cellarray, and also storing mapping information indicative of therelationship between the storage circuits and the redundancy cellarrays, the storage circuits outputting, when an address assigned to oneof the defective memory cells stored therein matches an input address, areplacement control signal for the defective memory cell on the basis ofthe result of matching, and the mapping information; and spare decoderseach to be activated by the replacement control signal supplied from thestorage circuits to thereby select a corresponding one of the redundancycell arrays.

[0012] Furthermore, the object of the invention is realized by a deviceas below.

[0013] A semiconductor storage device comprising:

[0014] a memory cell array having memory cells arranged in columns androws, the memory cell array being divided into a plurality of sub cellarrays; redundancy cell arrays each located adjacent to a correspondingone of the sub cell arrays; row decoders for each selecting acorresponding one of the rows of the memory cell array in accordancewith an input address; column decoders for each selecting acorresponding one of the columns of the memory cell array in accordancewith an input address; a plurality of storage circuits each including: aplurality of first storage elements for storing addresses assigned todefective memory cells included in the memory cell array; a plurality ofsecond storage elements for storing mapping information which indicatesthe relationship between the redundancy cell arrays and the storagecircuits; a plurality of comparators each for comparing the address of acorresponding one of the defective memory cells stored in acorresponding one of the first storage elements with an input address,and outputting, when the stored address matches the input address, asignal indicating that those addresses match each other; and a decoderfor decoding the mapping information stored in the second storageelements when each of the comparators has output the signal indicatingthat the addresses match each other; and spare decoders each to beactivated by the output signal of the decoder to thereby select acorresponding one of the redundancy cell arrays.

[0015] In the invention, defective cell can be saved in a reliablemanner even when they are located at only one area of the memory cellarray, by virtue of the structure in which the redundancy cell arraysand mapping information indicative of the relationship between circuitsfor storing defective cells are stored in the circuits. Moreover, in theinvention, the area efficiency of the redundancy circuit can be enhancedby reducing the number of redundancy cell arrays necessary to savedefective cells.

[0016] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0017] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0018]FIG. 1 is a block diagram illustrating an essential part of a DRAMaccording to the embodiment of the invention;

[0019]FIG. 2 is a block diagram illustrating a specific structure of asub cell array incorporated in FIG. 1;

[0020]FIG. 3 is a circuit diagram showing a sub cell array and itsperipheral circuit incorporated in FIG. 1;

[0021]FIG. 4 is a circuit diagram showing a fuse set incorporated inFIG. 1;

[0022]FIG. 5 is a circuit diagram illustrating the structure of adecoder incorporated in FIG. 4;

[0023]FIG. 6 is a block diagram illustrating a modification of the fuseset;

[0024]FIG. 7 is a block diagram illustrating an arrangement of sub cellarrays and spare elements;

[0025]FIG. 8 is a block diagram showing a modification of thearrangement of the sub cell arrays and the spare elements;

[0026]FIG. 9 is a block diagram showing another modification of thearrangement of the sub cell arrays and the spare elements;

[0027]FIG. 10 is a block diagram showing a further modification of thearrangement of the sub cell arrays and the spare elements;

[0028]FIG. 11 is a block diagram showing yet another modification of thearrangement of the sub cell arrays and the spare elements;

[0029]FIG. 12 is a block diagram showing another modification of thearrangement of the sub cell arrays and the spare elements;

[0030]FIG. 13 is a block diagram showing a furthermore modification ofthe arrangement of the sub cell arrays and the spare elements;

[0031]FIG. 14 is a block diagram illustrating an example of aconventional redundancy system; and

[0032]FIG. 15 is a block diagram illustrating another example of aconventional redundancy system.

DETAILED DESCRIPTION OF THE INVENTION

[0033] The embodiment of the invention will be described with referenceto the accompanying drawings.

[0034]FIG. 1 shows an essential structure of a DRAM according to theembodiment of the invention. A memory cell array 1 is divided into subcell arrays (SCA) 11 (m, n) arranged in a matrix of M (rows)×N(columns). Specifically, the memory cell array 1 is divided into 128 subcell arrays 11 (m, n) (m: 0-7, n: 0-15) which are obtained by arranging8 sub cell arrays in each row (M=8) and 16 sub cell arrays in eachcolumn (N=16). The division unit of the sub cell arrays 11 is determinedon the basis of, for example, the number of columns which cansimultaneously transmit data to a data line, and the number of rows (thenumber of word lines) which are connected to a single sense amplifierarray and included in continuous bit lines. In this embodiment, thedivision unit is also a saving unit in which defective memory cells aresaved by a single spare element (redundancy cell array). However, it ispossible to save a plurality of defective sub cell arrays using onespare element.

[0035] The 8 sub cell arrays 11 arranged in each row constitute a singlebank, and in total, 16 banks Bn (n: 0-15) are provided in thisembodiment. Further, 16 sub arrays arranged in each column constitute asub array column, and in the FIG. 1 case, 8 sub cell array columns Cm(m: 0-7) are arranged. A row decoder circuit 3 for decoding a rowaddress RA supplied from the outside of the cell array 1 is located ateach row-directional end of the cell array 1, while a column decodercircuit 2 m for decoding a column address CA supplied from the outsideof the array 1 is located at each sub cell array column Cm. The memorycells are selected using these row decoder circuits 3 and the columndecoder circuits 2 m.

[0036] Each sub cell array 11 includes a plurality of word lines WL,dummy word lines DWL, and a plurality of column selecting lines CSLperpendicular to the word lines, as is shown in FIG. 2. Although thecapacitance of each sub cell array 11 is optional, in this embodiment,16 column selecting lines CSL are included in each sub cell array 11.Further, as shown in FIG. 2, sense amplifier arrays 6 are arranged onthe opposite sides of each sub cell array 11 for reading data from bitlines selected by the column selecting lines CSL. These sense amplifierarrays 6 are of a so-called shared sense amplifier system which iscommonly used by adjacent sub cell arrays. However, they are not limitedto the shared sense amplifier system, but may have a structure in whicha sense amplifier array is provided for each sub cell array.

[0037] A spare element 12 (m, n) as a redundancy cell array is locatedat a row-directional end of each sub cell array 11, and a spare columnselecting line SCSLm (m: 0-7) is located parallel to the columnselecting lines CSL for selecting the spare element 12.

[0038]FIG. 3 specifically illustrates the structure shown in FIG. 2. InFIG. 3, the spare element 12 has a pair of redundancy bit lines BL andbBL (hereinafter, “b” indicates an inverted signal). However, the spareelement is not limited to this structure, but may have a plurality ofpairs of redundancy bit lines. Memory cells MC and dummy memory cellsDMC similar to those of each sub cell array 11 are connected to theredundancy bit lines BL and bBL which constitute the spare element 12.These memory cells MC and dummy cells DMC are respectively selected bythe word lines WL and the dummy word line DWL which extend from the subcell array 11.

[0039] As is shown in FIG. 1, the column selecting lines CSL and thespare column selecting lines SCSL extend through the 16 (=N) sub cellarrays 11 and spare elements 12. The column decoder circuits (CD) 2 forselecting the column selecting lines CSL are commonly provided for the16 (=N) sub cell arrays 11 arranged in each column. A spare columndecoder (SCD) 9 m is located adjacent to each column decoder circuit 2.The spare column decoders (SCD) 9 m drive the spare column selectinglines SCSL commonly connected to the 16 (=N) spare elements 12.

[0040] As is shown in FIG. 3, the pair of bit lines BL and bBL of thesub cell arrays 11 and the spare elements 12 are connected to senseamplifiers (SA) which constitute the sense amplifier arrays 6. A columnselecting switch circuit (SW) 7 is connected between a correspondingsense amplifier 6 and a corresponding pair of data lines DQ and bDQ. Thecolumn selecting switch circuits (SW) 7 are connected to the columnselecting lines CSL and spare column selecting lines SCSL andselectively on/off controlled by signals therefrom. When reading data,data transmitted through the bit lines BL and bBL are amplified by thesense amplifier (SA), and output to the data lines DQ and bDQ when theswitch circuit 7 is turned on.

[0041] As is shown in FIG. 1, this embodiment employs 16 (=N) fuse sets5 n (n: 0-15) whose number is identical to the number of therow-directional sub cell arrays 11 (i.e. the number of banks). Each fuseset 5 ₀-5 ₁₅ stores an address assigned to a defective memory cell(which will be referred to as a “defective address”), and compares anaddress supplied from the outside. If the comparison result indicatesthat they are identical to each other, a corresponding spare element 12outputs a signal for instructing replacement of a correspondingdefective column. This signal is supplied to the spare column decoder ofa corresponding sub cell array, and an inverted signal of the signal issupplied to the column decoder of the corresponding sub cell array.Further, each fuse set 5 ₀-5 ₁₅ stores information (mapping information)on the relationship between themselves and the 8 spare column selectinglines SCSL₀-SCSL₇. Particulars will be described later.

[0042] This embodiment employs the same number (M×N) of spare elements12 as the number (M×N) of sub cell arrays 11, and the same number offuse sets 5 as the number of the column-directional sub cell arrays 11.However, the invention is not limited to this. In other words, thepresent invention differs from the conventional case in that the formeruses mapping information indicative of the relationship between the fusesets and the spare elements. In the conventional case, one fuse set isprepared for one spare element. On the other hand, in this embodiment,each fuse set is made to correspond to an optional spare element by themapping information. As a result, the number of required fuse sets canbe set smaller than the number of spare elements. Moreover, even wheredefective cells uniformly disperse or locally gather, they can be saved.The relationship between the number Nfs of fuse sets and the number ofspare elements in the present invention is expressed by

N _(fs) ≦M×N

[0043] Each fuse set 5 ₀-5 ₁₅ has 8 output lines 8 ₀-8 ₇. When rewritinga defective column selecting line, one of the output lines 8 ₀-8 ₇ isactivated. The output lines 8 ₀-8 ₇ of each fuse set 5 ₀-5 ₁₅ areconnected to 8 replacement control signal lines 4 ₀-4 ₇, respectively,thereby constituting a wired OR circuit. When replacing a defectivecell, one of the 8 replacement control signal lines 4 ₀-4 ₇ is set athigh level in accordance with a high level signal output from one of thefuse sets 5 ₀-5 ₁₅. When one of the replacement control signal lines 4₀-4 ₇ is at high level, one of the spare column selecting lines SCSL isselected by one of the spare column decoders (SCD) to which the highlevel signal is supplied. At the same time, those of the column decoders(CD) to which the high level signal is supplied via an inverter circuit22 cause the column selecting lines CSL of a corresponding sub cellarray 11 to be non-selected. Thus, the 8 replacement control signallines 4 ₀-4 ₇ control the 8 column decoder circuits 2 ₀-2 ₇ and thespare column decoders 9 ₀-9 ₇ adjacent to the column decoder circuits.

[0044] The operation of the replacement control signal lines 4 will bedescribed in more detail. The first replacement control signal line 4 ₀selectively activates the column decoder circuit 2 ₀ and the sparecolumn decoder 9 ₀ adjacent thereto. To this end, the input terminal ofeach column decoder (CD) included in the column decoder circuit 2 ₀ isconnected to the replacement control signal line 4 ₀ via the inverter22, while the input terminal of the spare column decoder (SCD) 9 ₀ isdirectly connected to the replacement control signal line 4 ₀.Accordingly, when the replacement control signal line 4 ₀ is at highlevel, the spare column decoder 9 ₀ is activated, whereas the columndecoder circuit 2 ₀ is inactivated. As a result, the spare columnselecting line SCSL₀ is selected in place of the column selecting lineCSL selected by the column decoder circuit 2 ₀, thereby reading datafrom the spare elements 12 connected to the line SCSL₀.

[0045] Similarly, the second et seq. replacement control signal lines 4₁ 4 ₂, . . . selectively activate the column decoder circuits 2 ₁, 2 ₂,. . . and the spare column decoders 9 ₁ 9 ₂, . . . adjacent thereto.When in this structure, the spare column selecting line SCSL has beenselected in an optional sub cell array, the column selecting line SCL isinactivated, thereby replacing a defective cell with a spare cell.

[0046]FIG. 4 shows one of the fuse sets 5 ₀-5 ₁₅ of FIG. 1 in detail. Adescription will be given of the one fuse set since they have the samestructure. The fuse set 5 comprises an address designating fuse circuit501 for storing a defective address in the memory cell array 1, anenable fuse circuit 502 for storing whether or not the fuse set 5 isused, and a mapping fuse circuit 503 which pre-stores the address of oneof the 8 spare column selecting lines SCSL corresponding to the fuse set5.

[0047] The address designating fuse circuit 501 has 11 fuses FS. Seven(1)-(7), for example, of the fuses FS are used to designate a minimumunit of the column address. The remaining 4 fuses FS (8)-(11) are usedto select 16 spare elements 12 using a single spare column selectingline SCSL. More specifically, the address designating fuse circuit 501includes address information for designating a defective memory cell ina corresponding sub cell array 11, and address information for selecting16 banks Bn (n: 0-15). The mapping fuse circuit 503 has three fuses FS(13)-(15) necessary to select the 8 spare column selecting lines SCSLm.In other words, the mapping fuse circuit 503 stores address informationfor selecting one of the 8 sub cell array columns Cm (m: 0-7) arrangedin the row direction.

[0048] Each fuse FS included in the fuse circuits 501-503 is connectedin series to a pre-charging PMOS transistor Qp and a selecting NMOStransistor Qn between a power voltage Vcc and a ground potential Vss. Aconnection node N between the PMOS transistor Qp and the NMOS transistorQn is an output node. After the PMOS transistor Qp is turned on topre-charge the output node N with the power voltage Vcc, the PMOStransistor Qp is turned off and the NMOS transistor Qn is turned on,thereby reading fuse data. If the fuse FS is cut as indicated by thebroken line, a high-level voltage (Vcc) is output from the output nodeN, whereas if the fuse FS is not cut, a low-level voltage (Vss) isoutput from the output node N.

[0049] A signal output from the fuse circuit 501 is supplied to anaddress match detecting circuit 504 formed of a plurality of comparatorsCMP, together with column addresses a0-a6 and addresses b0-b3. Theaddresses b0-b3 are necessary to select 16 spare elements 12 using asingle spare column selecting line SCSL. The address match detectingcircuit 504 detects whether or not data contained in the output signalof the fuse circuit 501 matches the column addresses a0-a6 and addressesb0-b3. The output signals of the address match detecting circuit 504 andthe enable fuse circuit 502 are supplied to an AND gate 505. The outputterminal of the AND gate 505 outputs a Match signal 507 (i.e. an enablesignal for replacing a defective cell) indicating that an addresssupplied from the outside matches fuse information. The

[0050] The Match signal 507 is supplied to a decoder 506. The decoder506 is connected to three output signal lines 508 ₁, 508 ₂ and 508 ₃ ofthe mapping fuse circuit 503. When the Match signal 507 has beenactivated, the decoder 506 decodes the output signal of the mapping fusecircuit 503. As a result, one of the 8 output lines 8 of the decoder 506is activated and serves as a replacement control signal for activatingone of the replacement control signal lines 4.

[0051] The address designating fuse circuit 501 has 11 fuses, the enablefuse circuit 502 has one fuse, and the mapping fuse circuit has threefuses. This is, however, merely an example. The number of fuses of theaddress designating fuse circuit 501 is increased or decreased inaccordance with the capacitance of the sub cell array 11 and thecapacitance of the bank, while the number of fuses of the mapping fusecircuit 503 is increased or decreased in accordance with the number ofsub cell array columns. The enable fuse circuit 502 can have a pluralityof fuses.

[0052]FIG. 5 shows an example of the decoder 506. The decoder 506 isformed of 8 AND gates G1-G8 for receiving three signals output from thefuse circuit 503, their inverted signals, and the Match signal 507. Thereplacement control signal is output from the AND gates G1-G8.

[0053] In the above-described embodiment, one spare element 12 isprovided for each of the 128 sub cell arrays 11, and 16 fuse sets areprovided for the entire array 1 to enable saving of 16 sub cell arrays11. Furthermore, each fuse set 5 has the address designating fusecircuit 501 for storing a defective address, and the mapping fusecircuit 503 for storing mapping information indicating how to make the16 fuse sets 5 correspond to the 8 sub cell array columns Cm. One of the8 replacement control signal lines 4 is selected from the mappinginformation so that each fuse set 5 will be assigned to an optional subcell array column Cm. Accordingly, even when defective portions dispersein the memory cell array or gather in a certain area thereof, the 16fuse sets 15 can be used effectively.

[0054] Specifically, suppose that the memory cell array I shown in FIG.1 has 16 defective cells along one column selecting line CSL of the subcell array column C₀. In this case, all the 16 fuse sets 5 ₀-5 ₁₅ storemapping information for activating the replacement control signal line 4₀, and the 16 defective cells along the one column selecting line can besaved by the 16 fuse sets 5 ₀-5 ₁₅.

[0055] The advantage of the redundancy system of this embodiment will bedescribed in detail, referring to FIGS. 14 and 15 which show theconventional redundancy systems. In FIGS. 14 and 15, elements similar tothose in FIG. 1 are denoted by corresponding reference numerals.

[0056] In the conventional system shown in FIG. 14, a spare element 12(m, n) is provided for each of 128 sub cell arrays 11 (m, n). Thisstructure is similar to the present invention. However, in the FIG. 14case, a fuse set group 601 (601 ₀-601 ₇) is provided for each sparecolumn selecting line SCSL. Each fuse set group 601 has 16 fuse sets 602(602 ₀-602 ₁₅) which correspond to 16 spare elements 12 arranged alongthe spare column selecting line SCSL. For example, the fuse set 602 ₀corresponds to the spare element 12 (1,0), while the fuse set 602 ₁₅corresponds to the spare element 12 (1, 15). Thus, one spare element 12is made to correspond to one fuse set 602. Supposing that the number ofaddresses in this case is the same as in the embodiment, the number offuses is 1024 (={7 (for addresses)+1 (for enable)}×16×8). This number is4.3 times greater the number of fuses used in the embodiment.

[0057] Since in the FIG. 14 conventional case, the 128 spare elements 12can be replaced with defective cells, the degree of saving is high as inthe embodiment. However, where the average number of defective cellswhich will occur in one chip is supposed to be about 10, the number offuse sets actually used is about 10. Thus, a large number of fuse setsare not used to save defective cells. The defective cell savingefficiency is very low for the area occupied by the redundancy circuiton the chip.

[0058] In the other conventional case shown in FIG. 15, a single spareelement 12 is commonly provided for a plurality of sub cell arrays 11arranged in each column. Fuse sets 701 ₀-701 ₇ are provided for sub cellarray columns C₀-C₇, respectively. In this case, the number of fuses isas small as 64 (={7 (for addresses) +1 (for enable)}×8). However,supposing that the average number of defective cells which will occur inone chip is about 10 as stated above, the 8 spare elements 12 is too fewto obtain a sufficient saving efficiency and a sufficient yield ofchips.

[0059] On the other hand, in the case of the embodiment of the presentinvention, the number of spare elements 12 is 128 in the memory cellarray 1, while the number of fuses is 240 (={7 (for addresses)+4 (forspare element selection)+1 (for enable)+3 (for mapping)}×16). Thus, thenumber of fuses in the embodiment is much smaller than in the FIG. 14case. Moreover, rewriting of a defective cell can be performed byselecting any one of the 128 spare elements. This means that the savingefficiency is high.

[0060]FIG. 6 shows a modification of the fuse set. When there are aplurality of defective cells along a certain column selecting line inthe above-described embodiment, address information on each defectivecell is supplied to the mapping fuse circuit 503 so as to program thecircuit to deal with the defective cells using a plurality of fuse sets.On the other hand, where all memory cells along a single columnselecting line are defective, they can be saved by a single fuse set ifthe structure of the fuse set shown in FIG. 4 is modified as shown inFIG. 6. In FIG. 6, a fuse circuit 511, an AND gate 513 and an OR gate514 are added to the fuse set shown in FIG. 4. The fuse circuit 511 isan enable fuse circuit which has a single fuse and is adapted toindicate whether or not the fuse set is being used. The AND gate 513receives that one of the output signals of the match detecting circuit504, which corresponds to a bank address designating circuit section 501b. The output signals of the AND gate 513 and the fuse circuit 511 aresupplied to the OR gate 514, which in turn supplies its output to theAND gate 505.

[0061] If all memory cells along a certain column selecting line aredefective in the above structure, the fuse of the fuse circuit 511 of acorresponding fuse set is cut. In the structure, it is not necessary toprogram the bank address designating circuit 501 b of the addressdesignating fuse circuit 501.

[0062] When in this structure, a defective column address is input, theMatch signal 507 is made high by the output signal of the fuse circuit511 irrespective of the bank address. In other words, when all cellsalong a single column selecting line are defective, they can be savedusing a single fuse set. Accordingly, defective cells can be saveddepending on the circumstances such as the number of them or theirplaces.

[0063] Although one spare element 12 is provided for each sub cell array11 in the embodiment, the invention is not limited to this. Thearrangement or the number of spare elements 12 can be modified invarious manners as shown in FIGS. 7-12.

[0064]FIG. 7 shows an example in which one spare element 12 is providedfor a plurality of sub cell arrays 11 arranged in each row. In thiscase, a single spare element 12 is used to save any defective cellincluded in the sub cell arrays 11 arranged in each row. The number ofspare elements 12 is obtained by dividing the number (M×N) of sub cellarrays 11 by N.

[0065] Since the FIG. 7 structure employs a small number of spareelements, it is effective when the density of defective cells is low.This structure can reduce the area of the redundancy system withoutdegrading its saving efficiency.

[0066]FIG. 8 shows an example in which one spare element 12 is commonlyprovided for a plurality of sub cell arrays 11 arranged in each column.In this case, defective cells included in sub cell arrays 11 arrangedalong a certain column selecting line CSL can be replaced with a spareelement 12 at a time. Further, this structure enables reduction of thenumber of fuses included in one fuse set, the number of comparatorcircuits, and the number of AND gates, thereby reducing the requiredchip area and enabling a high speed operation.

[0067]FIG. 9 shows an example in which a spare element 12 is interposedbetween each sub cell array 11 and a corresponding row decoder 3. If inthis structure, an input/output circuit is provided in the vicinity ofthe row decoders, data can be transferred at high speed between theinput/output circuit and a selected spare element.

[0068]FIG. 10 shows an example in which a row decoder is interposedbetween each sub cell array 11 and a corresponding spare element 12.This structure can provide the same advantage as the FIG. 9 structure.

[0069]FIG. 11 shows an example in which a spare element 12 is providedin a middle portion of sub cell arrays 11 arranged in each row. Thisstructure can also provide the same advantage as the FIG. 9 structure.

[0070] In FIGS. 9-11, each spare elements 12 can be provided for subcell arrays 11 arranged in a corresponding column, as in the FIG. 8case.

[0071]FIG. 12 shows a case where the number of spare elements 12 differsbetween portions of the memory cell array 1. Specifically, two spareelements 12 are provided for a certain sub cell array 11, while onespare element 12 is provided for another sub cell array 11. In general,a defective portion is liable to occur in an area, where the continuityof a pattern is interrupted, such as an end portion of the chip or ofthe memory cell array. A plurality of defective portions can be saved byarranging a plurality of spare elements adjacent to a sub cell arraylocated in an area, where the continuity of a pattern is interrupted,such as an end of the chip or of the memory cell array as shown in FIG.12.

[0072]FIG. 13 shows a case where the number of spare elements differs inaccordance with the capacitance of a sub cell array. For example, thereis a memory device, such as a memory with a parity bit or a DRAMconformable to a Rambus, in which a memory cell array is divided intosub cell arrays of different capacitances. In such a memory cell array,the density of defective cells differs in accordance with thecapacitance of each sub cell array. In a memory cell array 11 shown inFIG. 13, a sub cell array 11 a has a capacitance of 160 K bits, while asub cell array 11 b has a capacitance of 128 K bits. In this case, thedegree of occurrence of defective cells is higher in the sub cell array11 a than in the sub cell array 11 b. Accordingly, two spare elementsare provided for the sub cell array 11 a, and one spare element is forthe sub cell array 11 b.

[0073] Since in the above structure, plural spare elements are providedonly for a sub cell array in which defective cells of a high densitywill occur, the number of required spare elements can be minimized,thereby enhancing the saving efficiency of defective cells.

[0074] The invention can be modified in various manners. For example,although in the embodiment, a description has been given to a case wherea defective column selecting line, i.e. a defective bit line, isreplaced with a spare element, the invention is also applicable to acase where a defective word line is replaced with a spare element.

[0075] Furthermore, although the embodiment uses a fuse as anon-volatile storage element that constitutes a defective addressstorage circuit, any other nonvolatile semiconductor storage elementsuch as a ROM, EPROM, EEPROM, etc. can be used.

[0076] In addition, the invention is applicable not only to asemiconductor storage device as one unit, but also to a storage devicemerged with a logic circuit, etc.

[0077] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

1. A semiconductor storage device comprising: a memory cell array havingmemory cells arranged in columns and rows, the memory cell array beingdivided into a plurality of sub cell arrays; redundancy cell arrays eachlocated adjacent to a corresponding one of the sub cell arrays; rowdecoders for each selecting a corresponding one of the rows of thememory cell array in accordance with an input address; column decodersfor each selecting a corresponding one of the columns of the memory cellarray in accordance with an input address; a plurality of storagecircuits for storing addresses assigned to defective memory cellsincluded in the memory cell array, and also storing mapping informationindicative of the relationship between the storage circuits and theredundancy cell arrays, the storage circuits outputting, when an addressassigned to one of the defective memory cells stored therein matches aninput address, a replacement control signal for the defective memorycell on the basis of the result of matching, and the mappinginformation; and spare decoders each to be activated by the replacementcontrol signal supplied from the storage circuits to thereby select acorresponding one of the redundancy cell arrays.
 2. A device accordingto claim 1, wherein the sub cell arrays are arranged in a number M ofrows and a number N of columns, and the number of the storage circuitsis equal to or less than M×N.
 3. A device according to claim 1, whereineach of the storage circuits has a plurality of output terminals foroutputting the replacement control signal, the output terminals of eachof the storage circuits being connected to each other by a plurality ofreplacement control signal lines, and constituting a wired OR circuit.4. A device according to claim 31 wherein each of the spare decoders isconnected to a corresponding one of the replacement control signallines, and each of the column decoders corresponding to said each of thespare decoder is connected to said corresponding one of the replacementcontrol signal lines via an inverter circuit.
 5. A device according toclaim 1, wherein the sub cell arrays are arranged in a number M of rowsand a number N of columns, each of the redundancy cell arrays is locatedcorresponding to each of the sub cell arrays, and the storage circuitsinclude mapping information indicative of the relationship between thestorage circuits and the number M of rows of redundancy cell arrays, thenumber of the storage circuits being N.
 6. A device according to claim5, wherein the number of the storage circuits is M, each of the Mstorage circuits having a number N of output terminals for selecting acorresponding one of the M rows of redundancy cell arrays.
 7. A deviceaccording to claim 1, wherein the storage circuits each include: anaddress designating fuse circuit for storing an address assigned to adefective memory cell; a mapping fuse circuit for storing mappinginformation indicative of the relationship between the storage circuitsand the redundancy cell arrays; an address match detecting circuit fordetecting whether the address stored in the address designating fusecircuit matches an input address; and a decoder for decoding the outputsignal of the mapping fuse circuit when the address match detectingcircuit has output a signal indicating that those addresses match eachother, thereby creating the replacement control signal.
 8. A deviceaccording to claim 1, wherein the sub cell arrays are arranged in anumber M of rows and a number N of columns, and those of the sub cellarrays which are arranged in each row constitute a bank.
 9. A deviceaccording to claim 8, wherein the storage circuits each include: anaddress designating fuse circuit for storing an address assigned to adefective memory cell; a mapping fuse circuit for storing mappinginformation indicative of the relationship between the storage circuitsand the redundancy cell arrays; a bank address designating fuse circuitfor storing an address assigned to a corresponding bank; an enable fusecircuit indicating whether or not said each storage circuit should beused; a first address match detecting circuit for detecting whether theaddress stored in the address designating fuse circuit matches an inputaddress; a second address match detecting circuit for detecting whetherthe address stored in the bank address designating fuse circuit matchesan input address; a first AND circuit for receiving a signal output fromthe first address match detecting circuit and indicating that theaddresses match each other; a OR circuit for receiving the output signalof the first AND circuit and the output signal of the enable fusecircuit; a second AND circuit for receiving a signal output from thesecond address match detecting circuit and indicating that the addressesmatch each other, and for also receiving the output signal of the ORcircuit; and a decoder for decoding the output signal of the mappingfuse circuit in response to the output signal of the second AND circuit,thereby creating the replacement control signal.
 10. A device accordingto claim 1, wherein each-of the redundancy cell arrays is locatedadjacent to the sub cell arrays of a corresponding row.
 11. A deviceaccording to claim 1, wherein each of the redundancy cell arrays islocated adjacent to the sub cell arrays of a corresponding column, andis commonly used between the sub cell arrays of the correspondingcolumn.
 12. A device according to claim 1, wherein each of theredundancy cell arrays is interposed between the sub cell arrays of acorresponding row and a corresponding one of the row decoders.
 13. Adevice according to claim 1, wherein each of the row decoders isinterposed between a corresponding one of the redundancy cell arrays anda corresponding one of the sub cell arrays.
 14. A device according toclaim 1, wherein each of the redundancy cell arrays is located in themiddle of the sub cell array of a corresponding row.
 15. A deviceaccording to claim 1, wherein the redundancy cell arrays are locatedadjacent to that one of the sub cell arrays which is situated at an endof the memory cell array.
 16. A device according to claim 1, wherein thememory cell array has a first sub cell array of a large capacitance, anda second sub cell array of a smaller capacitance than the first sub cellarray, the redundancy cell arrays being located adjacent to the firstsub cell array, and one of the redundancy cell arrays being locatedadjacent to the second sub cell array.
 17. A semiconductor storagedevice comprising: a memory cell array having memory cells arranged incolumns and rows, the memory cell array being divided into a pluralityof sub cell arrays; redundancy cell arrays each located adjacent to acorresponding one of the sub cell arrays; row decoders for eachselecting a corresponding one of the rows of the memory cell array inaccordance with an input address; column decoders for each selecting acorresponding one of the columns of the memory cell array in accordancewith an input address; a plurality of storage circuits each including: aplurality of first storage elements for storing addresses assigned todefective memory cells included in the memory cell array; a plurality ofsecond storage elements for storing mapping information which indicatesthe relationship between the redundancy cell arrays and the storagecircuits; a plurality of comparators each for comparing the address of acorresponding one of the defective memory cells stored in acorresponding one of the first storage elements with an input address,and outputting, when the stored address matches the input address, asignal indicating that those addresses match each other; and a decoderfor decoding the mapping information stored in the second storageelements when each of the comparators output the signal indicating thatthe addresses match each other; and spare decoders each to be activatedby the output signal of the decoder to thereby select a correspondingone of the redundancy cell arrays.
 18. A device according to claim 17,wherein each of the storage circuits has a plurality of output terminalsfor outputting the output signal of the decoder, the output terminals ofeach of the storage circuits being connected to each other by aplurality of replacement control signal lines, and constituting a wiredOR circuit.
 19. A device according to claim 18, wherein each of thespare decoders is connected to a corresponding one of the replacementcontrol signal lines, and each of the column decoders corresponding tosaid each of the spare decoder is connected to said corresponding one ofthe replacement control signal lines via an inverter circuit.
 20. Adevice according to claim 17, wherein the memory cell array has a firstsub cell array of a large capacitance, and a second sub cell array of asmaller capacitance than the first sub cell array, two or more of theredundancy cell arrays being located adjacent to the first sub cellarray, and one of the redundancy cell arrays being located adjacent tothe second sub cell array.
 21. A semiconductor storage devicecomprising: a memory cell array having memory cells arranged in columnsand rows; a plurality of redundancy cell arrays provided in the memorycell array; and a plurality of storage circuits each for storing anaddress assigned to a defective memory cell included in the memory cellarray, and also storing mapping information indicative of therelationship between the storage circuits and the redundancy cellarrays, the storage circuits outputting, when an address assigned to oneof the defective memory cells stored therein matches an input address, areplacement control signal for the defective memory cell on the basis ofthe mapping information.
 22. A device according to claim 21, wherein thenumber of the storage circuits is smaller than the number of theredundancy cell arrays.
 23. A device according to claim 21, furthercomprising spare decoders each to be activated by the replacementcontrol signal supplied from a corresponding one of the-storagecircuits, thereby selecting a corresponding one of the redundancy cellarrays.
 24. A device according to claim 21, wherein each of the storagecircuits has a plurality of output terminals for outputting thereplacement control signal, the output terminals of each of the storagecircuits being connected to each other by a plurality of replacementcontrol signal lines, and constituting a wired OR circuit.
 25. A deviceaccording to claim 24, wherein each of the spare decoders is connectedto a corresponding one of the replacement control signal lines, and eachof the column decoders corresponding to said each of the spare decoderis connected to said corresponding one of the replacement control signallines via an inverter circuit.
 26. A device according to claim 21,wherein the storage circuits each include: an address designating fusecircuit for storing an address assigned to a defective memory cell; amapping fuse circuit for storing mapping information which indicates therelationship between the redundancy cell arrays and the storagecircuits; an address match detecting circuit for detecting whether theaddress stored in the address designating fuse circuit matches an inputaddress; and a decoder for decoding the output signal of the mappingfuse circuit when the address match detecting circuit has output asignal indicating that those addresses match each other, therebycreating the replacement control signal.